The present invention relates to an amplifier circuit and an A/D converter.
For a circuit technique for implementing a discrete-time analog signal processing circuit such as a pipeline A/D converter, a variable gain amplifier, etc., a switched capacitor amplifier circuit is known. The switched capacitor amplifier circuit has a capacitor, an amplifier, and a plurality of switches, and samples or holds an input voltage in the capacitor by switching the plurality of switches.
For a technique for reducing the power consumption of such a switched capacitor amplifier circuit, a switched operational amplifier is known. In this technique, of two operating modes (a sample mode and an amplifier mode) of the switched capacitor amplifier circuit, during a sample mode period during which the operational amplifier is not used, the operational amplifier is turned off. Also, there is proposed a switched operational amplifier using, in combination with the above technique, a boost amplifier technique for increasing an open loop gain of the amplifier by increasing the output impedance.
In a switched operational amplifier, when the rise time of the amplifier where the operational amplifier is switched from off to on is long, the period during which the operational amplifier is turned off is reduced and thus a power-saving effect cannot be obtained, causing a problem that an increase in speed cannot be supported.
Normally, on/off switching of the switched operational amplifier is performed by switching a bias voltage to a current source transistor of the amplifier. However, this bias voltage node may be provided with a large decoupling capacitance to keep the bias voltage constant. Therefore, when switching from off to on is performed, the large capacitance needs to be charged, resulting in a long rise time.
In view of this, a technique is proposed in which instead of switching a bias voltage node provided with a large capacitance, by switching the connection of an output node of a boost amplifier with a small parasitic capacitance, the rise time is reduced (see, for example, Imran Ahmed and David A. Johns, “A 50-MS/s (35 mW) to 1-kS/s (15 μW) Power Scaleable 10-bit Pipelined ADC Using Rapid Power-On Opamps and Minimal Bias Current Variation”, IEEE Journal of Solid-State Circuits, December 2005, Vol. 40, No. 12).
When such related art is implemented with a low voltage, to ensure a signal amplitude, a large-sized transistor is used for a cascode transistor of a main amplifier. Hence, a large parasitic capacitance is generated between an output node of a boost amplifier and an output node of the main amplifier, resulting in a long activation time of the main amplifier. This is caused because a voltage change at the output node of the main amplifier occurred by an on/off switching operation of the amplifier is transmitted to the output node of the boost amplifier by parasitic capacitance coupling. Therefore, to reduce the activation time using the configuration according to the related art, there is a need to increase the driving capability of the boost amplifier, which causes a problem that a power-saving effect cannot be obtained.